1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly, to a semiconductor integrated circuit device, in which an interlevel dielectric layer has voids between narrow-spaced wiring lines in a same wiring layer, and a fabrication method of the device.
2. Description of the Prior Art
FIG. 1 shows a conventional, typical multilevel wiring structure of a semiconductor integrated circuit device.
In FIG. 1, a semiconductor substructure 101 has an insulating layer 101a on its main surface. The substructure 101 is typically comprised of a silicon substrate and a field oxide formed on the substrate, or of a silicon substrate and an interlevel dielectric layer formed on or over the substrate. Various semiconductor elements such as transistors are formed in the substructure 101.
A conductive layer 102 is formed on the insulating layer 101a. An anti-reflection layer 103 is formed on the conductive layer 102. The conductive layer 102 and the anti-reflection layer 103 constitute a first-level wiring layer W1.
An interlevel dielectric layer 104 is formed on the insulating layer 101a to cover the underlying wiring layer W1. The first-level wiring layer W1 is entirely buried in the dielectric layer 104.
Another conductive layer 105 is formed on the underlying interlevel dielectric layer 104. Another anti-reflection layer 106 is formed on the wiring layer 105. The conductive layer 105 and the anti-reflection layer 106 constitute a second-level wiring layer W2.
The conventional multilevel wiring structure of a semiconductor integrated circuit device shown in FIG. 1 is fabricated by the following process steps.
First, as shown in FIG. 2A, the semiconductor substructure 101 including specific semiconductor elements is prepared.
Next, two conductive layers are formed to be stacked on the insulating layer 101a of the substructure 101 by sputtering or the like. The stacked conductive layers are then patterned by photolithography and etching processes to thereby form the conductive layer 102 and the anti-reflection layer 103. The anti-reflection layer 103 serves to prevent irradiated exposure light from being reflected by the conductive layer 102 during the photolithography process. The state at this stage is shown in FIG. 2A.
Subsequently, the interlevel dielectric layer 104 is formed on the insulating layer 101a by Chemical Vapor Deposition (CVD) or the like in such a way that the conductive layer 102 and the anti-reflection layer 103 are entirely buried in the dielectric layer 104. The surface of the layer 104 is then planarized by a Chemical/Mechanical Polishing (CMP) process. The state at this stage is shown in FIG. 2B.
Further, two conductive layers are formed to be stacked on the interlevel dielectric layer 104 by sputtering or the like. The stacked conductive layers are then patterned by photolithography and etching processes to thereby form the conductive layer 105 and the anti-reflection layer 106. The anti-reflection layer 106 serves to prevent irradiated exposure light from being reflected by the conductive layer 105 during the photolithography process.
Following this, the interlevel dielectric layer 107 is formed on the interlevel dielectric layer 104 by CVD or the like in such a way that the conductive layer 105 and the anti-reflection layer 106 are entirely buried in the dielectric layer 107. Thus, the two-level wiring structure is fabricated as shown in FIG. 2C.
With the conventional semiconductor integrated circuit device shown in FIG. 1, the lower interlevel dielectric layer 104 electrically insulates (a) any one of wiring lines of the lower wiring layer W1 from another and (b) the upper wiring layer W2 from the lower wiring layer W1. The upper interlevel dielectric layer 107 electrically insulates any one of wiring lines of the upper wiring layer W2 from another.
Further, there is a problem that the circuit operation speed is very difficult to be increased due to parasitic capacitance between the adjoining wiring lines of the lower and upper wiring layers W1 and W2. Recently, this problem has become serious because submicron-order gaps between the wiring lines has been becoming popular.
The parasitic capacitance increases or decreases proportional to the dielectric constant of the interlayer dielectric layer 104 or 107 and inversely proportional to the gap or lateral distance between the adjoining wiring lines. Therefore, to increase the circuit operation speed while the integration level of circuits is kept high, the dielectric constant of the interlayer dielectric layers 104 and 107 needs to be decreased.
To realize the dielectric constant decrease, another conventional multilevel wiring structure of a semiconductor integrated circuit device as shown in FIG. 3 was developed. In this structure, miniaturized particles are mixed into a material for an interlevel dielectric layer and then, the particles are selectively etched out, resulting in the interlevel dielectric layer including a lot of micro voids. The voids are dispersed in the whole interlevel dielectric layer.
In FIG. 3, an insulating cap layer 208 is formed on a main surface of a semiconductor substructure 201. The substructure 201 is typically comprised of a silicon substrate and a field oxide formed on the substrate, or of a silicon substrate and an interlevel dielectric layer formed on or over the substrate. Various semiconductor elements such as transistors are formed in the substructure 201.
An interlevel dielectric layer 204 is formed on the insulating cap layer 208. The layer 204 has a lot of voids 213 dispersed within the whole layer 204. An insulating cap layer 209 is formed on the interlevel dielectric layer 204.
A wiring layer W1, which is formed by a patterned conductive layer 202, is located on the insulating cap layer 209. An insulating cap layer 210 is formed on the exposed cap layer 209 to cover the wiring layer W1.
An interlevel dielectric layer 207 is formed on the cap layer 210. The layer 207 has a lot of voids 215 dispersed within the whole layer 207. An insulating cap layer 212 is formed on the interlevel dielectric layer 207. The wiring layer 202 or W1 and the cap layer 210 are entirely buried in the interlevel dielectric layer 207.
Another wiring layer W2, which is formed by a patterned conductive layer 205, is located on the insulating cap layer 212.
The conventional multilevel wiring structure of a semiconductor integrated circuit device shown in FIG. 3 is fabricated by the following process steps.
First, as shown in FIG. 4A, the semiconductor substructure 201 is prepared. Next, a silicon dioxide (SiO.sub.2) layer serving as the insulating cap layer 208 is formed on the main surface of the substructure 201 by a CVD or sputtering process.
A SiO.sub.2 -system, low-temperature-setting glass material, into which aluminum (Al) micro particles 214 with a small diameter in the order of submicrons have been mixed, is coated on the surface of the insulating cap layer 208, and is then cured under heat. Thus, an insulating layer 204a including the Al micro particles 214 is formed on the cap layer 208, as shown in FIG. 4B.
Next, using an etchant (e.g., NaOH or KOH) having an etching action to the Al particles 214 and no etching action to the glass material, the insulating layer 204a is etched to selectively remove the particles 214 in the cap layer 208, resulting in the voids 213. Thus, the interlayer dielectric layer 204 including the voids 213 is formed, as shown in FIG. 4C.
Following this, the insulating cap layer 209 is formed on the interlayer dielectric layer 204 by a CVD or sputtering process, as shown in FIG. 4D.
A metal layer is formed on the insulating cap layer 209, and then patterned by photolithography and etching processes to thereby form the wiring layer 202 or W1, as shown in FIG. 4E.
Further, the interlayer dielectric layer 207, the insulating cap layer 212, and the wiring layer 205 or W2 are successively formed on the interlayer dielectric layer 204 by the same process steps as those shown in FIGS. 4A to 4E. Thus, the two-level wiring structure as shown in FIG. 3 is fabricated.
With the conventional semiconductor integrated circuit device shown in FIG. 3, there are following problems.
First, the micro particles 214 are dispersed into the insulating material 204a and then, they are selectively etched away from the material 204a to form the voids 213. Further, the upper and lower cap layers 209 and 208 are necessarily formed in order to bury the opening voids 213 and 215, thereby planarizing the surface of the interlevel dielectric layer 204. Therefore, a problem that the fabrication process sequence is complicated occurs.
Second, the voids 213 are dispersed in the whole dielectric layer 204. Therefore, to use a CMP process, which is effective for surface planarization, the thin cap layer 212 needs to be selectively polished away. This is caused by the following reason.
Since the voids 215 are dispersed in the entire dielectric layer 207, the voids 215 located in the upper region of the dielectric layer 204 are exposed or opened during a CMP process. Water, which is used for the CMP process, tends to enter the opened voids 215 to reach the underlying wiring layer 202 through the unopened voids 215 and the cap layer 210. This water will cause corrosion damage to the wiring layer 210, thereby degrading the reliability of the semiconductor integrated circuit device.
To cope with the corrosion damage, the cap layer 212 needs to be very thick. However, this will degrade the fabrication yield or productivity.
Third, at present when the miniaturization of wiring lines have been progressed, the micro particles 214 tend not to be located in the narrow gaps or spaces between the wiring lines where the parasitic capacitance decrease is necessary and tend to be located in the wide gaps or spaces between the wiring lines where the parasitic capacitance decrease is not necessary. Thus, there is a problem that the parasitic capacitance is not always decreased for the miniaturized wiring lines.
A method of forming a multilevel wiring structure of a semiconductor integrated circuit device was disclosed in the Japanese Examined Patent Publication No. 7-114236 published in December 1995.
In this method, after a first insulating layer is formed on a substrate, a metal layer is formed on the first insulating layer. The metal layer is selectively etched to form a wiring layer on the first insulating layer. Subsequently, a second insulating layer is formed by sputtering on the first insulating layer to cover the wiring layer in such a way that at least a part of the gaps or spaces between the wiring lines of the wiring layer includes a void or voids.
The material for the second insulating layer is not deposited in the narrow gaps or spaces between the wiring lines during the sputtering process, thereby forming voids in the narrow gaps or spaces in the second insulating layer. The voids have a larger height than that of the wiring lines. In other words, the tops of the voids protrude from the wiring lines.
With the method of forming the wiring structure disclosed in the Japanese Examined Patent Publication No. 7-114236, since the tops of the voids formed in the second insulating layer protrude from the wiring lines, the voids tend to be exposed or opened during a CMP process. Therefore, there is the same problem relating to the CMP process as in the conventional wiring structure shown in FIG. 3.